The mip.SEIE bit is in fact composed of two different bits, a
hardware-writeable one and another software-writable one. The behavior
of CSR set and clear operations is modified for the particular case of
this bit. To emulate it properly we would need to special case all of
the CSR set and clear functions to ignore the hardware-writeable bit.

Instead of duplicating the whole logic, this commit simply omit the
hardware-writeable bit, making it invisible to the virtualized firmware.
In practice this is not really an issue as we force the external
supervisor interrupts to be delegated, so the firmware should not be in
charge of devices generating such interrupts (because we don't want to
emulate them).

This commit fixes the hangs with the Linux shell payload when the Sstc
exension is not present. This can be tested with the following config
parameters on a sufficiently modern QEMU:

```
[qemu]
machine = "virt"
cpu = "sifive-u54,sstc=false"
```

This PR implements proper MTI virtualization. For that purpose it lays
out the foundations of full interrupt virtualization, i.e. it lets
Miralis manage the `mip` bits and inject interrupts rather than relying
on the hardware physical interrupts.

For now all physical M-mode timer interrupts are still assumed to be
caused by the firmware and update the virtual `mip.MTIP` bit. If we need
out-of-band MTI we should implement a mechanism for distinguishing the
cause of a timer interrupt, most likely simply checking if the virtual
`mtimecmp` deadline passed or not.

This commit implements proper MSI virtualization. For that purpose it
virtualizes the list of pending MSI in the virtual CLINT. When a vCPU
sends an MSI to another core the virtual CLINT triggers a physical MSI
to signal the core that a virtual interrupt should be injected. If a
vCPU triggers an MSI on the current core then a virtual interrupt is
injected directly without causing a physical interrupt.

This is an important first step toward allowing out-of-band (host) MSI,
which are required by some security policies for cross-caches flushes.

This commit adds three integration tests to exercise the new machine
timer (MTI) and software (MSI) interrupts. The tests exercise:

1. (clint_interrupt) the MTI, including proper reset and multiple
   interrupts delivery.
2. (clint_interrupt_multihart) the MSI across cores.
3. (clint_interrupt_priority) the relative priority of interrupts
   delivery between MSI and MTI.


Co-authored-by: Sofia <[email protected]>

Update the documentation to clarify that only M-mode interrupts are
virtualized, and that S-mode interrupts are explicitly out-of-scope.

Also removes some white-spaces in the doc ASCII art of the relevant
section, as those can cause rendering issue on the website.

The new crate can be extended in the future to hold more test helpers,
such as macros to generate proper interrupt handlers. For now it is
limited to clint functionalities and assumes the QEMU virt platform (it
is not meant to be a general-purpose library).